Digital Back- End Engineer

Physical Design Engineer

We are hiring ASIC Physical Design Engineers at both mid-level (6+ years) and experienced (10+ years) levels to take our custom silicon from RTL to GDSII and into the heart of Optiver's global trading systems. You'll work alongside engineers with decades of combined back-end and tapeout experience, driving the digital back-end flow for latency-critical networking and trading blocks – closing timing, power and area on advanced FinFET process nodes – and partnering closely with our FPGA, software and trading teams to bring new silicon from concept to working system.

Hardware Engineers at Optiver build hardware-based trading systems ranging from low-latency algorithms to high-bandwidth computation. They own all aspects of the development process – from ideation to implementation – creating bespoke solutions to our most complex trading problems. Their systems have little room for failure; they add to the stability of the market, not detract from it. Working in close collaboration with software engineers and traders, our hardware engineers deeply understand our trading problems and create dynamic, well-architected systems that make an impact in a matter of days and weeks rather than months and years.

Optiver is building with cutting-edge AI technology in one of the most competitive, data-rich landscapes in the world: financial markets. Our hardware engineers use AI to move faster across the development process – from design exploration and scripting to closing complex implementation challenges – while retaining full ownership of the designs and decisions it supports.

WHAT YOU'LL DO:

• Own the full RTL-to-GDSII flow – synthesis, floorplanning, power planning, placement, clock tree synthesis, routing, extraction, timing closure, EM/IR analysis and physical verification (DRC/LVS) through to signoff and tapeout.
• Build and continuously improve Optiver's digital back-end tool flow and methodology for fast, repeatable delivery of high-performance designs.
• Close timing, power and area on latency-critical networking and trading blocks, including high-speed I/O and SerDes-adjacent paths.
• Integrate third-party analog and digital IP, with a focus on 10Gb or faster networking interfaces.
• Shape the direction for the adoption and integration of ASIC solutions across our trading and network infrastructure.
• Research new low-latency techniques, process nodes and platforms, and identify opportunities to integrate them into our trading systems.
• Partner with FPGA developers, software engineers, traders and infrastructure engineers to rapidly deliver integrated systems, and help grow the skills and capabilities of the hardware team.

WHO YOU ARE:

We have multiple roles open across two levels – mid-level Physical Design Engineers (6+ years) and experienced Physical Design Engineers (10+ years) – and we are looking for engineers with:

• Hands-on physical design experience taking digital designs through the full RTL-to-GDSII flow, with one or more successful tapeouts.
• Proven experience implementing designs on FinFET process nodes, including the advanced-node effects that come with them (parasitics, congestion, variability and EM/IR margins).
• Deep expertise across the digital back-end flow.
• A strong command of static timing analysis and constraints (SDC), and the ability to debug complex timing and signal-integrity issues.
• Fluency with industry-standard implementation and signoff tools, and a willingness to move between toolchains as our flow evolves.
• Strong scripting skills in TCL and Python for flow development, automation and debug.
• Experience integrating third-party IP (analog and digital), ideally including high-speed networking interfaces of 10Gb or faster.
• A Bachelor's or Master's degree in Electrical/Computer Engineering, Computer Science or a related technical field.
• A pragmatic engineering mindset, a hands-on approach and a genuine passion for solving hard problems.

NICE TO HAVE:

• Experience with process-node selection and evaluation.
• Previous experience interacting with EDA vendors, IP vendors and foundries.
• Some front-end RTL design and verification experience.
• Experience supporting silicon bring-up and debugging.
• A track record of taking silicon from tapeout into production systems.